1. Field of the Invention
The present invention relates to a boosting circuit having a charge pump circuit.
2. Description of Related Art
Referring to FIG. 1, a boosting circuit according to a conventional technique will be described. As one example, a boosting circuit disclosed in U.S. Pat. No. 6,577,514 will be described.
The boosting circuit according to the conventional technique includes a charge pump circuit 202, a clamping regulator 206, an auxiliary charge pump circuit 208, and an N-channel transistor 214. The clamping regulator 206 compares a division voltage 204 divided from an output voltage 200 of the charge pump circuit 202 with a Vbias voltage (1.3V), and outputs a comparison result 212 to a gate of the N-channel transistor 214. A drain of the N-channel transistor 214 is connected to a power supply VDD, and a source thereof is connected to the charge pump circuit 202 as a power supply line 216. In addition, the clamping regulator 206 operates by using an output 210 (Va) of the auxiliary charge pump circuit 208.
Next, an operation of the boosting circuit according to the conventional technique will described.
(1) At a start of an operation of the charge pump circuit 202, the output voltage 200 is nearly 0V, and the division voltage 204 is lower than the “Vbias=1.3V” of clamping regulator 206. Accordingly, an output voltage (the comparison result 212) of the clamping regulator 206 is Va. That is, a gate voltage of the N-channel transistor 214 is Va, and a potential difference between the gate and the source of the N-channel transistor 214 is “(Va)−(Va−Vt)=Vt” (a threshold voltage of the N-channel transistor 214). Consequently, the N-channel transistor 214 is turned on, a current is supplied to the charge pump circuit 202, and the charge pump circuit 202 continues a boosting operation.
(2) In the boosting operation of the charge pump circuit 202, when the division voltage 204 becomes higher than the “Vbias=1.3V” supplied to the clamping regulator 206, the comparison result 212 becomes a voltage Vb lower than the Va. In this case, the potential difference between the gate and the source in the N-channel transistor 214 is the “(Vb)−(Va−Vt)=Vt”, and becomes lower than the threshold voltage Vt. Accordingly, the N-channel transistor 214 is turned off or nearly turned off and an amount of current supplied to the charge pump circuit 202 reduces. In this case, the charge pump circuit 202 cannot continue the boosting operation and the output voltage 200 decreases.
(3) When the output voltage 200 of the charge pump circuit 202 has decreased, the division voltage 204 also decreases. When the division voltage 204 becomes lower than the “Vbias=1.3V” supplied to the clamping regulator 206, the voltage level of the comparison result 212 returns to the voltage Va. That is, the gate voltage of the N-channel transistor 214 becomes Va, and the potential difference between the gate and the source in the N-channel transistor 214 becomes “(Va)−(Va−Vt)=Vt” (the threshold voltage of the N-channel transistor 214). Consequently, the N-channel transistor 214 is turned on, a current is supplied to the charge pump circuit 202, and the charge pump circuit 202 starts the boosting operation again.
(4) When continuing the boosting operation to set the state (2), the charge pump circuit 202 becomes the state (3) again. After repeating this operation, the output voltage of the charge pump circuit 202 will be in an approximately-constant level.
When the charge pump circuit 202 starts the boosting operation again in the above-mentioned state (3), a large instantaneous pass-through current flows from a power supply wiring to a drive circuit for driving a boost capacitor. In addition, charge and discharge currents flow to and from the boost capacitor in the charge pump circuit 202. In this manner, a voltage of the power supply line 216 of the charge pump circuit 202 decreases, and the potential difference between the gate and the source in the N-channel transistor 214 becomes larger than the threshold value of the N-channel transistor 214. That is, when the charge pump circuit 202 restarts the boosting operation, a current supply ability of the N-channel transistor 214 becomes large and thus the boosting operation ability of the charge pump circuit 202 is improved only for a short period. Consequently, a large current (hereinafter, to be referred to as a peak current) flows from the power supply wiring to the charge pump circuit 202 via the N-channel transistor 214.
FIG. 2 is a diagram showing a temporal change of a current flowing from the charge pump circuit 202 according to the conventional technique to the power supply terminal 216. Referring to FIG. 2, the current flowing from the charge pump circuit 202 to the power supply terminal 216 approximately has a value of 0 A at time T1 when the boosting circuit does not operate; however, the peak current of 230 mA flows at time T2 when the operation starts. As described above, when the charge pump circuit 202 starts the boosting operation, the large peak current flows to a power supply wiring and a GND wiring.
Generally, in an integrated circuit, various types of circuits such as a memory circuit, an analog circuit, and a logic circuit are connected to the power supply wiring or the GND wiring. When a large current I1 flows between these circuits and the power supply wiring, the voltage drop (of I1×R) occurs because of a power supply wiring resistance R. Or, when a large current I2 flows between these circuits and the GND wiring, the voltage rise (of I2×R2) occurs because of a GND wiring resistance R2. When the logic circuit is connected to the power supply wiring, the voltage of the power supply wiring drops and the voltage of the GND wiring rises. Thus, the power supply voltage supplied to the logic circuit becomes a voltage lower by “I1×R”, and the GND voltage becomes a voltage higher by “I2×R2”, resulting in a narrow power supply voltage margin. When the power supply voltage margin is smaller, an operation speed of the logic circuit sometimes decreases and a calculation result is sometimes reversed. For example, when an SRAM is connected to portions where the voltage of the power supply wiring dropped and the voltage of the GND wiring rose, a data retention state of a memory cell of the SRAM may be destroyed.
Since the miniaturizing progress in the present integrated circuit and accordingly cross-section areas of the power supply wiring and the GND wiring are reduced, wiring resistances tend to increase. Thus, the voltage drop of the power supply wiring and the voltage rise of the GND wiring are intensified because of the large peak current generated in the boosting circuit, and the power supply voltage margin to the circuit is further narrowed. In addition, since the peak current is temporarily generated, the power supply voltage becomes unstable. When the power supply voltage margin is narrowed and the power supply voltage becomes more unstable (a fluctuation) as described above, possibility of malfunction and functional deterioration is further increased.